This clocking module features two joined integer dividers, offering divisions from 2 through to 9, and capable of running at audio rates.
The clock source can be selected from either the external Clk socket or internal Bus (to be further developed). Divider B can alternately be clocked from the output of Divider A to allow longer divisions. Reset comes from the Rst socket, internal Bus or manual push-button. Both Clock and Reset pass through input comparators with threshold c.+1V. Outputs are 0V low, c.+10V high.
Checking the timing diagram, you can see that clocking occurs on the rising edge of a clock and outputs are high for 1 out of N clock cycles, where N is the Division selected. A Reset event sends both outputs high.
Current: +ve 15mA, -ve 0mA